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general description the max15036/max15037 high-frequency, dc-dc con- verters with an integrated n-channel power mosfet provide up to 3a of load current. the max15036 includes an internal power mosfet to enable the design of a nonsynchronous buck or boost topology power supply. the max15037 is for the design of a synchronous buck topology power supply. these devices operate from a 4.5v to 5.5v or 5.5v to 23v input voltage and offer the ability to set the switching frequency from 200khz to 2.2mhz with an external resistor. the voltage-mode architecture with a peak switch current-limit scheme provides stable operation up to a 2.2mhz switching frequency. the max15036 includes a clock output for driving a second dc-dc converter 180 out-of-phase and a power-on-reset ( reset ) output. the max15037 includes a power-good output and a synchronous rectifier driver to drive an external low-side mosfet in the buck converter config- uration for high efficiency. the max15036/max15037 protect against overcurrent conditions by utilizing a peak current limit as well as overtemperature shutdown providing a very reliable and compact power source for point-of-load regulation applications. additional features include synchroniza- tion, internal digital soft-start, and an enable input. the max15036/max15037 are available in a thermally enhanced, space-saving 16-pin tqfn (5mm x 5mm) package and operate over the -40c to +125c tem- perature range. applications xdsl modem power supplies automotive radio power supplies servers and networks ip phones/wlan access points features 4.5v to 5.5v or 5.5v to 23v input voltage range output voltage adjustable down to 0.6v (buck) or up to 28v (boost) 3a output current synchronous rectifier driver output (max15037) for higher efficiency resistor-programmable switching frequency from 200khz to 2.2mhz external synchronization and enable (on/off) inputs clock output for driving second converter 180 out-of-phase (max15036) integrated 150m high-side n-channel power mosfet power-on-reset output (max15036)/power-good output (max15037) short-circuit protection (buck)/maximum duty- cycle limit (boost) thermal-shutdown protection thermally enhanced 16-pin tqfn package dissipates 2.7w max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch ________________________________________________________________ maxim integrated products 1 15 16 14 13 6 5 7 drain fb 8 drain pgnd cko source 12 reset 4 12 11 9 bst/vdd en v l v+ bypass osc max15036 comp sgnd 3 10 sync ep* *exposed pad. thin qfn 5mm x 5mm top view + pin configurations ordering information 19-4222; rev 0; 7/08 for pricing delivery, and ordering information please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations continued at end of data sheet. part temp range pin-package max15036 ate+ -40c to +125c 16 tqfn-ep* max15037 ate+ -40c to +125c 16 tqfn-ep* selector guide part configuration features MAX15036ATE nonsynchronous buck or boost reset output, clock output max15037ate synchronous buck pgood output, synchronous fet driver + denotes a lead-free/rohs-compliant package. * ep = exposed pad.
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = v l = 5v or v+ = 5.5v to 23v, v en = 5v, t a = t j = -40c to +125c, unless otherwise noted. circuits of figures 5 and 6. typical values are at t a = t j = +25c.) (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to pgnd............................................................-0.3v to +25v bst/vdd, drain to sgnd ....................................-0.3v to +30v sgnd to pgnd .....................................................-0.3v to +0.3v bst/vdd to source...............................................-0.3v to +6v source to sgnd..................................................-0.6v to +25v source or drain maximum peak current...............5a for 1ms v l to sgnd ................-0.3v to the lower of +6v and (v+ + 0.3v) sync, en, dl, cko, osc, comp, fb to sgnd...............................................-0.3v to (v l + 0.3v) bypass, cko, osc, comp, fb, en, sync, reset , pgood maximum input current .................................50ma reset , pgood to sgnd ........................................-0.3v to +6v bypass to sgnd..................................................-0.3v to +2.2v v l and bypass short-circuit duration to sgnd ......continuous continuous power dissipation (t a = +70c) 16-pin tqfn (derate 33mw/c above +70c) ..........2666mw junction-to-case thermal resistance ( jc ) (note 1) 16-pin tqfn................................................................1.7c/w junction-to-ambient thermal resistance ( ja ) (note 1) 16-pin tqfn.................................................................30c/w operating temperature range .........................-40c to +125c junction temperature range ............................-65c to +150c storage temperature range .............................-65c to +150c lead temperature (soldering, 10s) .................................+300c note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units system specifications 5.5 23.0 input voltage range v+ v+ = v l 4.5 5.5 v v+ operating supply current i q v+ = 12v, v fb = 0.8v r osc = 10k ?, no switching 1.8 2.5 ma v+ standby supply current i stby v+ = 12v, v en = 0v, pgood (max15037), reset , cko unconnected (max15036), r osc = 10k 1 1.4 ma nonsynchronous (max15036), f sw = 1.25mhz, v+ = 12v, i out = 1.5a, v out = 3.3v 79 efficiency synchronous (max15037), f sw = 300khz, v+ = 12v, i out = 1.5a, v out = 3.3v 90 % v l regulator (v l )/bypass output (bypass) v l undervoltage lockout v uvlo v l falling 4.1 4.3 v v l undervoltage lockout hysteresis v hyst 137 mv v l output voltage v l v+ = 5.5v to 23v, i vl = 0 to 40ma 5.0 5.2 5.5 v v l regulator short-circuit current i vlshort v in = 5.5v 110 ma bypass output voltage v bypass v+ = v l = 5.2v, i bypass = 0 1.98 2 2.02 v bypass load regulation v bypass i bypass steps from 0 to 50a, v+ = v l = 5.2v 0 1.2 5 mv
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = v l = 5v or v+ = 5.5v to 23v, v en = 5v, t a = t j = -40c to +125c, unless otherwise noted. circuits of figures 5 and 6. typical values are at t a = t j = +25c.) (note 2) parameter symbol conditions min typ max units soft-start digital soft-start period internal 6-bit dac 4096 clock periods soft-start steps 64 steps error amplifier (fb and comp) fb to comp transconductance g m 1.20 1.8 2.75 ms fb input bias current i fb 250 na fb input voltage set point v fb 0.591 0.600 0.609 v comp sink-and-source current capability i comp 100 150 a internal mosfets on-resistance n-channel power mosfet r on v+ = v l = 5.2v, i sink = 100ma 0.150 0.302 leakage current i leak v en = 0v, v drain = 23v, source = pgnd 20 a minimum output current i out v out = 3.3v, v+ = 12v (note 3) 3 a peak current limit i limit 3.56 4.6 5.6 a on-resistance internal low-side switch r onlsw i switch = 50ma, v+ = v l = 5.2v 20 40 synchronous rectifier driver (dl) (max15037 only) on-resistance nmos r ondln i sink = 10ma 1 4 on-resistance pmos r ondlp i source = 10ma 1.9 5 peak sink current i idl_sink 1a peak source current i idl_source 0.75 a clock output (cko) (max15036 only) clock output-high level v ckoh v l = 5.2v, i source = 5ma 3.54 v clock output-low level v ckol v l = 5.2v, i sink = 5ma 0.4 v clock output phase delay with respect to source waveform cko phase r osc = 10k , sync = gnd (note 4) 115 degrees oscillator (osc)/synchronization (sync) r osc = 5.62k 2100 r osc = 41.2k 312 switching frequency f sw v+ = v l = 5.2v r osc = 10k 1130 1250 1380 khz minimum controllable on-time t on_min 120 ns maximum duty cycle d max f sw = 2.2mhz 82 87.5 %
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch 4 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = v l = 5v or v+ = 5.5v to 23v, v en = 5v, t a = t j = -40c to +125c, unless otherwise noted. circuits of figures 5 and 6. typical values are at t a = t j = +25c.) (note 2) parameter symbol conditions min typ max units sync frequency range (note 5) 200 2200 khz sync input to source rising- edge phase delay sync phase r osc = 10k , f sync = 1.2mhz (note 6) 65 degrees sync high threshold v synch 2.0 v sync low threshold v syncl 0.8 v sync input bias current i sync 250 na minimum sync high pulse width t sync_h 100 ns en, reset (max15036)/pgood (max15037) v ih 2.0 en threshold v il 0.8 v en input bias current i en 250 na reset threshold v th v fb = v out (note 7) 90 92.5 95 % v out pgood threshold v th v fb = v out (note 7) 90 92.5 95 % v out fb to reset or fb to pgood propagation delay t fd 3s reset active timeout period t rp 140 200 254 ms reset , pgood output voltage low v ol i sink = 3ma 0.4 v reset , pgood output leakage current i leak v+ = v l = 5.2v, v r eset or v pgood = 6v, v fb = 0.8v 2a thermal shutdown thermal shutdown t shdn temperature rising +170 c thermal-shutdown hysteresis 25 c note 2: 100% tested at t a = +25c and t a = +125c. limits from t a = -40c to +25c are guaranteed by design. note 3: output current may be limited by the power dissipation of the package. see the power dissipation section in the applications information section. note 4: from the rising edge of the source waveform to the rising edge of the cko waveform. note 5: sync input frequency is equal to the switching frequency. note 6: from the sync rising edge to source rising edge. note 7: reset goes high 200ms after v out crosses this threshold, pgood goes high after v out crosses this threshold.
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch _______________________________________________________________________________________ 5 max15036 buck efficiency vs. output current (v in = 5.5v, f sw = 2.2mhz) max15036 toc01 output current (a) efficiency (%) 2.0 1.5 1.0 0.5 10 20 30 40 50 60 70 80 90 0 03.0 2.5 v out = 2.5v v out = 3.3v max15036 buck efficiency vs. output current (v in = 12v, f sw = 2.2mhz) max15036 toc02 output current (a) efficiency (%) 10 20 30 40 60 50 70 80 0 v out = 2.5v v out = 3.3v 2.0 1.5 1.0 0.5 03.0 2.5 max15036 buck efficiency vs. output current (v in = 16v, f sw = 2.2mhz) max15036 toc03 output current (a) efficiency (%) 10 20 30 40 50 60 70 0 2.0 1.5 1.0 0.5 03.0 2.5 v out = 2.5v v out = 3.3v max15037 synchronous efficiency vs. output current (v in = 12v, f sw = 330khz, l = 15 h) max15036 toc04 output current (a) efficiency (%) 55 60 65 70 75 80 85 90 95 50 l = toko ds126c2-150m 2.0 1.5 1.0 0.5 03.0 2.5 v out = 2.5v v out = 3.3v v out = 1.2v max15037 synchronous efficiency vs. output current (v in = 12v, f sw = 2.2mhz, l = 4.7 h) max15036 toc05 output current (a) efficiency (%) 10 20 30 40 50 60 70 80 0 2.0 1.5 1.0 0.5 03.0 2.5 v out = 3.3v max15037 output voltage vs. output current (v in = 12v, v out = 3.3v, f sw = 2.2mhz) max15036 toc06 output current (a) output voltage (v) 3.0 2.5 1.5 2.0 1.0 0.5 3.294 3.295 3.296 3.297 3.298 3.299 3.300 3.301 3.292 3.293 0 v l output voltage vs. switching frequency max15036 toc07 switching frequency (khz) v l (v) 2100 1600 600 1100 5.155 5.160 5.165 5.170 5.180 5.175 5.185 5.190 5.150 100 v in = 23v v in = 5.5v typical operating characteristics (v+ = v l = 5.2v, t a = +25c, figures 5 and 6, unless otherwise noted.)
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v+ = v l = 5.2v, t a = +25c, figures 5 and 6, unless otherwise noted.) max15037 v l dropout voltage vs. switching frequency max15036 toc08 switching frequency (khz) v l dropout voltage (v) 2100 1600 600 1100 0.05 0.10 0.15 0.20 0.30 0.25 0.35 0.40 0 100 v+ = 5.5v v+ = 5.25v v+ = 5v switching frequency vs. r osc max15036 toc09 resistance (k ) frequency (khz) 60 50 40 30 20 10 1000 10,000 100 070 switching frequency vs. temperature max15036 toc10 temperature ( c) frequency (khz) 110 60 10 350 600 850 1100 1350 1600 1850 2100 2350 100 -40 r osc = 20k r osc = 40k r osc = 10k r osc = 6.04k max15037 line-transient response (i out = 1a, v in step = 14v to 21v) max15036 toc11 100 s/div v in 5v/div 0v 200mv/div v out v out = 3.3v max15037 load-transient response (i out = 0.5a to 3a) max15036 toc13 20 s/div v out 200mv/div 0a 1a/div i out v in = 12v v out = 3.3v max15037 load-transient response (i out = 0.2a to 1a) max15036 toc12 20 s/div v out 100mv/div 0a 500ma/div i out v in = 12v v out = 3.3v max15037 soft-start and shutdown (no load) max15036 toc14 1ms/div v out 1v/div 0v 0v 5v/div v en v in = 12v
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v+ = v l = 5.2v, t a = +25c, figures 5 and 6, unless otherwise noted.) max15037 soft-start and shutdown (i out = 2a) max15036 toc15 1ms/div v out 1v/div 0v 0v 5v/div v en v in = 12v v in startup waveform (en connected to v l ) (max15037) max15036 toc16 1ms/div v en 5v/div v out 2v/div v pgood 5v/div v in 10v/div reset timeout (max15036) max15036 toc17 40ms/div 10v/div v in v en v out v reset 5v/div 5v/div 2v/div max15036 externally synchronized switching waveform max15036 toc18 100ns/div 5v/div 5v/div 5v/div 0v 0v 0v 0v v sync v cko v source_master v source_slave 5v/div standby current vs. temperature max15036 toc19 temperature ( c) standby current (ma) 100 120 60 80 20 40 0 1.45 1.50 1.55 1.60 1.40 -40 -20 f sw = 2.2mhz r osc = 5.62k switching supply current (i sw ) vs. temperature max15036 toc20 temperature ( c) switching supply current (ma) 100 75 -25 0 25 50 10 20 30 40 50 60 70 80 0 -50 125 max15036 v out = 3.3v i out = 1a f sync = 2.2mhz f sync = 1.2mhz f sync = 600khz f sync = 300khz maximum output current vs. temperature max15036 toc21 temperature ( c) maximum output current (a) 60 110 10 3.30 3.40 3.50 3.55 3.60 3.65 3.70 3.75 3.25 3.35 3.45 -40 v in = 12v v out = 3.3v f sw = 1mhz
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch 8 _______________________________________________________________________________________ pin description pin name function 1, 2 drain internal power mosfet drain connection. buck converter operationuse the mosfet as a high-side switch and connect drain to the input supply. boost converter operation (max15036 only)use the mosfet as a low-side switch and connect drain to the inductor and diode junction. 3 comp transconductance error amplifier output. connect a compensation network from comp to sgnd or from comp to fb to sgnd (see the compensation section). 4 fb feedback input. connect a resistive divider from the output to fb to sgnd to set the output voltage. 5 osc switching frequency set input. connect a resistor r osc from osc to sgnd to set the switching frequency. when using external synchronization, program r osc so that (0.8 x f sync ) f sw ( 1.2 x f sync ). r osc is still required when external synchronization is used. 6 bypass reference bypass connection. bypass to sgnd with a 0.22f or greater ceramic capacitor. 7v+ input supply voltage. v+ can range from 5.5v to 23v. connect v+ and v l together for 4.5v to 5.5v input operation. bypass v+ to sgnd with a minimum of 0.1f ceramic capacitor. 8v l internal regulator output. bypass v l to sgnd with a 4.7f ceramic capacitor and to pgnd with a 0.1f ceramic capacitor. connect v+ to v l for 4.5v to 5.5v operation. cko clock output (max15036 only). cko is an output with the same frequency as the converters switching frequency and 115 out-of-phase. cko is used to synchronize the max15036 to other max15036/max15037s. 9 dl low-side synchronous rectifier driver (max15037 only). dl sources 0.7a and sinks 1a to quickly turn on and off the external synchronous rectifier mosfet. 10 sgnd signal ground 11 pgnd power ground. connect the rectifier diodes anode, the input capacitor negative terminal, the output capacitor negative terminal, and v l bypass capacitor negative terminal to pgnd. 12 source internal power mosfet source connection. buck converter operationconnect source to the switched side of the inductor as shown in figure 5. boost converter operation (max15036 only)connect source to pgnd. 13 sync external synchronization input. connect sync to an external logic-level clock to synchronize the max15036/ max15037. connect sync to sgnd when not used. reset open-drain active-low reset output (max15036 only). reset remains low while the converters output is below 92.5% of v out s nominal set point. when v out rises above 92.5% of its nominal set point, reset goes high after the reset timeout period of 200ms (typ). 14 pgood open-drain power-good output (max15037 only). pgood remains low while the output is below 92.5% of its nominal set point. 15 bst/vdd internal mosfet driver supply input. buck converter operationbootstrap flying capacitor connection. connect bst/vdd to an external ceramic capacitor and diode (see figure 5). boost converter operation (max15036 only)driver bypass capacitor connection. connect a low-esr 0.1f ceramic capacitor from bst/vdd to pgnd. 16 en enable input. a logic-low turns off the converter. a logic-high turns on the device. connect en to v l for an always-on application. ep exposed pad. connect to sgnd. solder ep to sgnd to enhance thermal dissipation.
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch _______________________________________________________________________________________ 9 ldo oscillator v+ drain sync 2v 1v q r 4-pulse skip r sense current-limit comparator v ref = 0.6v 0.925 x v ref 200mv 200ms delay v l = 5.2v bst/vdd v l source pgnd fb comp reset q adaptive bbm pwm comparator n2 150m 20 n3 g m f sw /4 n1 cko osc bypass en digital soft-start v ref max15036 sgnd figure 1. max15036 block diagram
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch 10 ______________________________________________________________________________________ ldo oscillator v+ drain sync 2v 1v q r 4-pulse skip r sense v ref = 0.6v 0.925 x v ref 200mv v l = 5.2v bst/vdd v l source pgnd dl vl fb comp pgood q adaptive bbm n2 150m 20 n3 g m f sw /4 n1 osc bypass en digital soft-start v ref max15037 sgnd current-limit comparator pwm comparator figure 2. max15037 block diagram
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch ______________________________________________________________________________________ 11 detailed description pwm controller the max15036/max15037 use a pulse-width modula- tion (pwm) voltage-mode control scheme. the max15036 is a nonsynchronous converter and uses an external low-forward-drop schottky diode for rectifica- tion. the max15037 is a synchronous converter and drives a low-side, low-gate-charge mosfet for higher efficiency. the controller generates the clock signal from an internal oscillator or the sync input when dri- ven by an external clock. an internal transconductance error amplifier produces an integrated error voltage at comp, providing high dc accuracy. the voltage at comp sets the duty cycle using a pwm comparator and an internal 1v p-p voltage ramp. at each rising edge of the clock, the converters high-side n-channel mosfet turns on and remains on until either the appropriate or maximum duty cycle is reached or the maximum current limit for the switch is detected. in the case of the max15036 boost operation, the mosfet is a low-side switch. during each on-time, the inductor current ramps up. during the second half of the switching cycle, the low-side switch turns off and forward biases the schottky diode. during this time, the drain voltage is clamped to 0.4v (v d ) above v out and the inductor provides energy to the output as well as replenishes the output capacitor charge. max15036 during each high-side mosfet on-time (figure 5), the inductor current ramps up. during the second half of the switching cycle, the high-side mosfet turns off and for- ward biases the schottky rectifier (d2 in figure 5). during this time, the source voltage is clamped to 0.5v below ground. the inductor releases the stored energy as its current ramps down, and provides current to the output. during the mosfet off-time, when the schottky rectifier is conducting, the bootstrap capacitor (c10 in figure 5) is recharged from the v l output. at light loads, the max15036 goes in to discontinuous conduction mode operation when the inductor current completely dis- charges before the next switching cycle commences. when the max15036 operates in discontinuous conduc- tion, the bootstrap capacitor can become undercharged. to prevent this, an internal low-side 20 switch (see n3 in figure 1) turns on, during the off-time, once every 4 clock cycles. this ensures that the negative terminal of the boot- strap capacitor is pulled to pgnd often enough to allow it to fully charge to v l , ensuring the internal power switch properly turns on. the operation of the bootstrap capaci- tor wake-up switch causes a small increase in the output voltage ripple at light loads. under overload conditions, when the inductor current exceeds the peak current limit of the internal switch, the high-side mosfet turns off quickly and waits until the next clock cycle. max15037 the max15037 is intended for synchronous buck oper- ation only. during the high-side mosfet on-time, the inductor current ramps up. when the mosfet turns off, the inductor reverses polarity and forward biases the schottky rectifier in parallel with the low-side synchro- nous mosfet. the source voltage is clamped to 0.5v below ground until the break-before-make time (t bbm ) of 25ns is over. after t bbm, the synchronous rec- tifier mosfet turns on. the inductor releases the stored energy as its current ramps down, and contin- ues providing current to the output. the bootstrap capacitor is also recharged from the v l output when the mosfet turns off. the synchronous rectifier keeps the circuit in continuous conduction mode operation even at light load. under overload conditions, when the inductor current exceeds the peak current limit of the internal switch, the high-side mosfet turns off and waits until the next clock cycle. the max15037, with the synchronous rectifier driver out- put (dl), has an adaptive break-before-make circuit to avoid cross conduction between the internal power mosfet and the external synchronous rectifier mosfet. when the synchronous rectifier mosfet is turning off, the internal high-side power mosfet is kept off until v dl falls below 0.97v. similarly, dl does not go high until the inter- nal power mosfet gate voltage falls below 1.24v. input voltage (v+)/internal linear regulator (v l ) all internal control circuitry operates from an internally reg- ulated nominal voltage of 5.2v (v l ). at higher input volt- ages (v+) of 5.5v to 23v, v l is regulated to 5.2v. at 5.5v or below, the internal linear regulator operates in dropout mode, where v l follows v+. depending on the load on v l , the dropout voltage can be high enough to reduce v l to below the undervoltage lockout (uvlo) threshold. for input voltages of lower than 5.5v, connect v+ and v l together. the load on v l is proportional to the switching frequency of the converter. see the v l output voltage vs. switching frequency graph in the typical operating characteristics . for an input voltage higher than 5.5v, use the internal regulator. bypass v+ to sgnd with a low-esr 0.1f or greater ceramic capacitor placed as close as possible to the max15036/max15037. current spikes from v l disturb the internal circuitry powered by v l . bypass v l with a low-esr 0.1f ceramic capacitor to pgnd and a low- esr 4.7f ceramic capacitor to sgnd.
max15036/max15037 enable en is an active-high input that turns the max15036/ max15037 on and off. en is a ttl-logic input with 2.0v and 0.8v logic-high and low levels, respectively. when en is asserted high, the internal digital soft-start cycle slowly ramps up the internal reference and provides some soft-start at the output. hysteresis provides immu- nity to the glitches during logic turn-on of the converter. large voltage variations at en can interrupt the soft-start sequence and can cause a latch-up. ensure that en remains high for at least 5ms once it is asserted. force en low to turn off the internal power mosfet and cause reset to go low (max15036) or cause pgood to go low (max15037). connect en to v l when not used. soft-start/soft-stop the max15036/max15037 include uvlo with hystere- sis to prevent chattering during startup. the uvlo cir- cuit holds the max15036/max15037 off until v+ reaches 4.5v and turns the devices off when v+ falls below 4.3v. the max15036/max15037 also offer a soft-start feature that reduces surge currents and glitches on the input during turn-on. during turn-on when the uvlo threshold is reached or en goes from low to high, the digital soft-start ramps up the reference (v bypass ) in 64 steps. during a turn-off (by driving en or v+ low), the reference is reduced to zero slowly. the soft-start and soft-stop periods (t ss ) are 4096 cycles of the internal oscillator. to calculate the soft-start/soft-stop period use the following equation: f sw is the switching frequency of the converter. oscillator/synchronization (sync)/clock output (clkout) the clock frequency (or switching frequency) is gener- ated internally and is adjustable through an external resistor connected from osc to sgnd. the relationship between r osc and f sw is: the adjustment range for f sw is from 200khz to 2.2mhz. connect a logic-level clock between 200khz to 2.2mhz at sync to externally synchronize the max15036/ max15037s oscillator (see figure 8). the max15036/ max15037 synchronize to the rising edge of the sync clock. the rising edge of the sync clock corresponds to the turn-on edge of the internal n-channel power mosfet with a fixed propagation delay. when operating the max15036/max15037 with an external sync clock, r osc must be installed. program the internal switching frequency so that (0.8 x f sync ) f sw (1.2 x f sync ). the minimum pulse width for f sync is 100ns. connect sync to sgnd if synchronization is not used. the cko output (max15036 only) is a logic-level clock with the same frequency as f sw and with 115 phase shift with respect to sync clock. two max15036s can be connected in a master/slave configuration for two- phase (180) interleaved operation. the cko output of the master drives the sync input of the slave to form a dual-phase converter. to achieve the 180 out-of-phase operation, program the internal switching frequency of both converters close to each other by using the same r osc value. when synchronizing the master-slave con- figuration using external clock, program the internal switching frequency using r osc close to the external clock frequency (f sync ) for 180 ripple phase operation (see figure 8). any difference in the internal switching frequency and f sync changes the phase delay. if both master and slave converters use the same power source, and share input bypass capacitors, the effec- tive switching frequency at the input is twice the switch- ing frequency of the individual converter. higher ripple frequency at the input capacitor means a lower rms ripple current into the capacitor. current limit the max15036/max15037 protect against output over- load and short-circuit conditions when operated in a buck configuration. an internal current-sensing stage develops a voltage proportional to the instantaneous switch current. when the switch current reaches 4.6a (typ), the power mosfet turns off and remains off until the next on cycle. during a severe overload or short-circuit condition when the output voltage is pulled to ground, the discharging slope of the inductor is v ds (the voltage across the syn- chronous fet), or v f (the voltage across the rectifying diode) divided by l. the short off-time does not allow the current to properly ramp down in the inductor, caus- ing a dangerous current runaway and possibly destruc- tion of the device. to prevent this, the max15036/ max15037 include a frequency foldback feature. when the current limit is detected the frequency is reduced to 1/4th of the programmed switching frequency. when the output voltage falls below 1/3rd of its nominal set point (v fb = 0.2v), the converter is turned off and soft-start cycle is initiated. this reduces the rms current sourced by the converter during the fault condition. r s f osc sw = 125 10 8 / t f ss sw = 4096 2.2mhz, 3a buck or boost converters with an integrated high-side switch 12 ______________________________________________________________________________________
at high input-to-output differential, and high switching frequency, the on-time drops to the order of 100ns. even though the max15036/max15037 can control the on-time as low as 100ns, the internal current-limit circuit may not detect the overcurrent within this time. in that case, the output current during the fault may exceed the current limit specified in the electrical characteristics table. the max15036/max15037 may still be p rotected against the output short-circuit fault through the overtemperature shutdown. however, the output switch current may be as high as 5.6a. if the minimum on-time for a given frequency and duty cycle is less than 200ns, choose the inductor with a saturation current of greater than 5.6a. power-on reset ( reset ) (max15036 only) reset is an active-low open-drain output that goes low when v out falls below 92.5% of its nominal set point. reset goes high impedance when v out rises above 92.5% of its nominal set point, the soft-start period is complete, and the 200ms (typ) timeout period has elapsed. connect a pullup resistor from reset to a logic voltage or to v l . the internal open-drain mosfet at reset can sink 3ma while providing a ttl-compati- ble logic-low signal. connect reset to sgnd or leave unconnected when not used. power-good (pgood) (max15037 only) pgood is an open-drain, active-high output that goes low when v out is below 92.5% of its nominal set point and goes high impedance when v out goes above 92.5% its nominal set point. connect a pullup resistor from pgood to a logic voltage or to v l . pgood can sink up to 3ma while still providing a ttl-compatible logic-low output. pulling en low forces pgood low. connect pgood to sgnd or leave unconnected when not used. thermal-overload protection during a continuous output short-circuit or overload condition, the die junction temperature in the max15036/max15037 can exceed its limit. the max15036/max15037 provide an internal thermal shut- down to turn off the device when the die temperature reaches +170c. a thermal sensor monitors the die temperature and turns the device on again when the temperature reduces by +25c. during thermal shut- down, the internal power mosfet shuts off, dl pulls to sgnd, v l shuts down, reset (max15036)/pgood (max15037) goes low, and soft-start resets. applications information setting the switching frequency the controller generates the switching frequency (f sw ) through the internal oscillator or the signal at sync (f sync ), when driven by an external oscillator. the switching frequency is equal to f sw or f sync . a resistor, r osc , from osc to sgnd sets the internal oscillator. the relationship between f sw and r osc is: where f sw is in hertz, and r osc is in ohms. for exam- ple, a 1.25mhz switching frequency is set with r osc = 10k . higher frequencies allow designs with lower inductor values and less output capacitance. consequently, peak currents and i 2 r losses are lower at higher switching frequencies, but core losses, gate- charge currents, and switching losses increase. rising clock edges on sync are interpreted as a syn- chronization input. if the sync signal is lost, the internal oscillator takes control of the switching rate, returning the switching frequency to that set by r osc . this main- tains output regulation even with intermittent sync sig- nals. when using an external synchronization signal, set r osc so that (0.8 x f sync ) f sw (1.2 x f sync ). buck converter use the internal n-channel power mosfet as a high- side switch to configure the max15036/max15037 as a buck converter. in this configuration, source is con- nected to the inductor, drain is connected to the input, and bst/vdd connects to the cathode of the bootstrap diode and capacitor. figures 5 and 6 show the typical application circuits for max15036/ max15037, respectively, in a buck configuration. r 125 10 f osc 8 sw = max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch ______________________________________________________________________________________ 13
max15036/max15037 effective input voltage range the max15036/max15037 can operate with input sup- plies ranging from 4.5v to 5.5v or 5.5v to 23v. the input voltage range (v+) can be constrained to a mini- mum by the duty-cycle limitations and to a maximum by the on-time limitation. the minimum input voltage is determined by: d max is the maximum duty cycle of 87.5% (typ). v drop1 is the total drop in the inductor discharge path that includes the diodes forward voltage drop (or the drop across the synchronous rectifier mosfet), and the drops across the series resistance of the inductor and pcb traces. v drop2 is the total drop in the induc- tors charging path, which includes the drop across the internal power mosfet, and the drops across the series resistance of the inductor and pcb traces. the maximum input voltage can be determined by: where t on_min = 100ns and f sw is the switching frequency. setting the output voltage for 0.6v or greater output voltages, connect a resistive divider from v out to fb to sgnd. select the fb to sgnd resistor (r2) from 1k to 10k and calculate the resistor from out to fb (r1) by the following equation: where v fb = 0.6v, see figure 3. for designs that use a type iii compensation scheme, first calculate r1 for stability requirements (see the compensation section) then choose r2 so that: see figure 4. inductor selection three key inductor parameters must be specified for operation with the max15036/max15037: inductance value (l), peak inductor current (i peak ), and inductor saturation current (i sat ). the minimum required induc- tance is a function of operating frequency, input-to-out- put voltage differential, and the peak-to-peak inductor current ( i p-p ). higher i p-p allows for a lower inductor value, while a lower i p-p requires a higher inductor value. a lower inductor value minimizes size and cost, improves large-signal and transient response, but reduces efficiency due to higher peak currents and higher peak-to-peak output voltage ripple for the same output capacitor. on the other hand, higher inductance increases efficiency by reducing the ripple current. resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels especial- ly when the inductance is increased without also allow- ing for larger inductor dimensions. a good compromise is to choose i p-p equal to 30% of the full load current. use the following equation to calculate the inductance: v in and v out are typical values so that efficiency is optimum for typical conditions. the switching frequency is set by r osc (see the setting the switching frequency section). the peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worse at the maximum input voltage. see the output capacitor selection section to verify that the worst-case output rip- ple is acceptable. the inductor saturation current is also important to avoid runaway current during continuous output short-circuit. at high input-to-output differential, and high switching frequency, the on-time drops to the order of 100ns. though the max15036/max15037 can control the on-time as low as 100ns, the internal current- limit circuit may not detect the overcurrent within this time. in that case, the output current during the fault may exceed the current limit specified in the electrical characteristics table. the overtemperature shutdown protects the max15036/max15037 against the output short-circuit fault. however, the output current may reach 5.6a. choose an inductor with a saturation current of greater than 5.6a when the minimum on-time for a given frequency and duty cycle is less than 200ns. input capacitors the discontinuous input current of the buck converter causes large input ripple current. the switching frequen- cy, peak inductor current, and the allowable peak-to- peak input voltage ripple dictate the input capacitance requirement. increasing the switching frequency or the inductor value lowers the peak-to-average current ratio yielding a lower input capacitance requirement. l v(vv) vi out in out nsw pp = ? ? i f r rv vv fb out fb 2 1 = ? rr v v out fb 12 1 = ? ? ? ? ? ? ? v v tf in max out on min sw _ _ = v vv d vv in min out drop max drop drop _ = + +? 1 21 2.2mhz, 3a buck or boost converters with an integrated high-side switch 14 ______________________________________________________________________________________
the input ripple comprises mainly of v q (caused by the capacitor discharge) and v esr (caused by the esr of the input capacitor). the total voltage ripple is the sum of v q and v esr . assume the input voltage ripple from the esr and the capacitor discharge is equal to 50% each. the following equations show the esr and capaci- tor requirement for a target voltage ripple at the input: where where i out is the output current, d is the duty cycle, and f sw is the switching frequency. use additional input capacitance at lower input voltages to avoid pos- sible undershoot below the uvlo threshold during transient loading. output capacitor selection the allowable output voltage ripple and the maximum deviation of the output voltage during step load cur- rents determine the output capacitance and its esr. the output ripple comprises of v q (caused by the capacitor discharge) and v esr (caused by the esr of the output capacitor). use low-esr ceramic or alu- minum electrolytic capacitors at the output. for alu- minum electrolytic capacitors, the entire output ripple is contributed by v esr . use the esr out equation to cal- culate the esr requirement and choose the capacitor accordingly. if using ceramic capacitors, assume the contribution to the output ripple voltage from the esr and the capacitor discharge to be equal. the following equations show the output capacitance and esr requirement for a specified output voltage ripple. where: i p-p is the peak-to-peak inductor current as calculated above and f sw is the individual converters switching frequency. the allowable deviation of the output voltage during fast transient loads also determines the output capaci- tance and its esr. the output capacitor supplies the step load current until the controller responds with a greater duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the convert- er. the high switching frequency of the max15036/ max15037 allows for a higher closed-loop bandwidth, thus reducing t response and the output capacitance requirement. the resistive drop across the output capacitors esr and the capacitor discharge causes a voltage droop during a step load. use a combination of low-esr tantalum and ceramic capacitors for better transient load and ripple/noise performance. keep the maximum output voltage deviation below the tolerable limits of the electronics being powered. when using a ceramic capacitor, assume an 80% and 20% contribu- tion from the output capacitance discharge and the esr drop, respectively. use the following equations to calculate the required esr and capacitance value: where i step is the load step and t response is the response time of the controller. the controller response time depends on the control-loop bandwidth. boost converter the max15036 can be configured for step-up conver- sion since the internal mosfet can be used as a low- side switch. use the following equations to calculate the inductor (l min ), input capacitor (c in ), and output capacitor (c out ) when using the converter in boost operation. esr v i c it v out esr step out step response q = = ? i vv v vf l vvv pp in out out in sw out ripple esr q ? = ? () ?+ _ esr v i c i 8vf esr p-p out p-p qsw = = i vv v vf l and d v v pp in out out in sw out in ? = ? () = esr v i i c idd vf esr out pp in out qsw = + ? ? ? ? ? ? = ? () ? 2 1 max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch ______________________________________________________________________________________ 15
max15036/max15037 inductor choose the minimum inductor value so the converter remains in continuous mode operation at minimum out- put current (i outmin ). where and i outmin = 0.25 x i out . the v d is the forward voltage drop of the external schottky diode, d is the duty cycle, and v ds is the volt- age drop across the internal switch. select the inductor with low dc resistance and with a saturation current (i sat ) rating higher than the peak switch current limit of 5.6a. input capacitor the input current for the boost converter is continuous and the rms ripple current at the input is low. calculate the capacitor value and esr of the input capacitor using the following equations. where where v drop is the total voltage drop across the inter- nal mosfet plus the voltage drop across the inductor esr. i p-p is the peak-to-peak inductor ripple current as calculated above. v q is the portion of input ripple due to the capacitor discharge and v esr is the contri- bution due to esr of the capacitor. output capacitor for the boost converter, the output capacitor supplies the load current when the main switch is on. the required output capacitance is high, especially at high- er duty cycles. also, the output capacitor esr needs to be low enough to minimize the voltage drop due to the esr while supporting the load current. use the follow- ing equation to calculate the output capacitor for a specified output ripple tolerance. i out is the load current, v q is the portion of the ripple due to the capacitor discharge, and v esr is the con- tribution due to the esr of the capacitor. d max is the maximum duty cycle at minimum input voltage. power dissipation the max15036/max15037 are available in thermally enhanced 16-pin, 5mm x 5mm tqfn packages that dissipate up to 2.7w at t a = +70c. when the die tem- perature reaches +170c, the max15036/max15037 shut down (see the thermal-overload protection sec- tion). the power dissipated in the device is the sum of the power dissipated from supply current (p q ), power dissipated due to switching the internal power mosfet (p sw ), and the power dissipated due to the rms cur- rent through the internal power mosfet (p mosfet ). the total power dissipated in the package must be lim- ited so the junction temperature does not exceed its absolute maximum rating of +150c at maximum ambi- ent temperature. the power dissipated in the switch is: p mosfet = i rms_mosfet x r on for the buck converter: i p-p is the peak-to-peak inductor current ripple. iid id rms mosfet out pp _ () =+ ? ? ? ? ? ? ? ? ? 2 2 12 c id vf out out max qsw = esr v i esr out = i vv d lf pp in drop sw ? = ? () esr v i esr pp = ? c id fv in pp sw q = ? 4 d vvv vvv out d in out d ds = +? +? l vd fv i min in sw out outmin = 2 2 2.2mhz, 3a buck or boost converters with an integrated high-side switch 16 ______________________________________________________________________________________
for the boost converter: the power lost due to switching the internal power mosfet is: t r and t f are the rise and fall times of the internal power mosfet measured at source. the power lost due to the switching quiescent current of the device is: p q = v in x i sw (max15036) the switching quiescent current (i sw ) of the max15036/max15037 is dependent on switching fre- quency. see the typical operating characteristics sec- tion for the value of i sw at a given frequency. in the case of the max15037, the switching current includes the synchronous rectifier mosfet gate-drive current (i sw-dl ). the i sw-dl depends on the total gate charge (q g-dl ) of the synchronous rectifier mosfet and the switching frequency. p q = v in x (i sw + i sw-dl ) (max15037) i sw-dl = q g-dl x f sw where the q g-dl is the total gate charge of the synchro- nous rectifier mosfet at v gs = 5v. the total power dissipated in the device is: p total = p mosfet + p sw + p q calculate the temperature rise of the die using the fol- lowing equation: t j = t c + (p total x jc ) jc is the junction-to-case thermal resistance equal to 1.7c/w. t c is the temperature of the case and t j is the junction temperature, or die temperature. the case- to-ambient thermal resistance is dependent on how well heat can be transferred from the pcb to the air. solder the underside exposed pad to a large copper gnd plane. if the die temperature reaches +170c the max15036/max15037 shut down and do not restart again until the die temperature cools by 25c. compensation the max15036/max15037 have an internal transcon- ductance error amplifier with an inverting input (fb) and output (comp) available for external frequency compensation. the flexibility of external compensation and high switching frequencies for the max15036/ max15037 allow a wide selection of output filtering components, especially the output capacitor. for cost- sensitive applications, use high-esr aluminum elec- trolytic capacitors. for size-sensitive applications, use low-esr tantalum or ceramic capacitors at the output. before designing the compensation components, first choose all the passive power components that meet the output ripple, component size, and component cost requirements. secondly, choose the compensation components to achieve the desired closed-loop band- width and phase margin. use a simple 1-zero, 2-pole pair (type ii) compensation if the output capacitor esr zero frequency (f zesr ) is below the unity-gain crossover frequency (f c ). use a 2-zero, 2-pole (type iii) compensation when the f zesr is higher than f c . buck converter compensation use procedure 1 to calculate the compensation net- work components when f zesr < f c . procedure 1 (see figure 3) calculate the f zesr and f lc double pole: calculate the unity-gain crossover frequency as: f f c sw = 20 f esr c f lc zesr out lc out = = 1 2 1 2 p vi tt f sw in out r f sw = + () 4 i pk =+ ? i i in pp 2 i dc =? ? i i in pp 2 i vv d lf pp in drop sw ? = ? () i vi v in out out in = ii+i+(ii d 3 rms_mosfet dc pk dc pk max 22 = ()) max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch ______________________________________________________________________________________ 17
max15036/max15037 if f zesr is lower than f c and close to f lc , use a type ii compensation network where r f c f provides a midband zero (f mid,zero ) and r f c cf provides a high-frequency pole. calculate the modulator gain (g m ) at the crossover frequency. where v osc is the 1v p-p ramp amplitude and v fb = 0.6v. the transconductance error amplifier gain at f c is: g e/a = g m x r f the total loop gain at f c should be equal to 1: g m = g e/a = 1 or place a zero at or below the lc double pole: place a high-frequency pole at f p = 0.5 x f sw . therefore c cf is: procedure 2 (see figure 4) when using a low-esr ceramic-type capacitor as the output capacitor, the esr frequency is much higher than the targeted unity-gain crossover frequency (f c ). in this case, type iii compensation is recommended. type iii compensation provides a low-frequency pole ( dc) and two pole-zero pairs. the locations of the zero and poles should be such that the phase margin peaks at f c . the is a good number to get approximate- ly 60 of phase margin at f c . however, it is important to place the two zeros at or below the double pole to avoid conditional stability. first, select the crossover frequency so that: calculate the lc double-pole frequency, f lc : where: with r f 10k . calculate c a for a target unity crossover frequency, f c : place a second zero, f z2 , at 0.2 x f c or at f lc , whichev- er is lower. c c (2 0.5 f r c ) -1 cf f sw f f = place a second pole (f 1 2rc at 1/2 the switchin g fre q uenc y . p2 fcf = ) r 1 2c r 1 a a = ? f z2 r a = 1 2 fc zesr a place a pole f at f p zesr () . 1 = 1 2r c aa c 2flc v a c out osc = vr in f c f = 1 2 0.75 f r lc f placeazerof 1 2rc at 0.75 f z ff = lc f 1 2lc lc out = f f 20 c sw f f f f 5 c z p c == c 1 r cf = fsw f c 1 2r f f = f lc r v (esr 2 f l)v v v g esr f osc c out in m = + fb g v in v osc esr esr 2 f c l) v fb v out m = + ( 2.2mhz, 3a buck or boost converters with an integrated high-side switch 18 ______________________________________________________________________________________
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch ______________________________________________________________________________________ 19 v ref v out r1 comp r2 r f c f c cf g m figure 3. type ii compensation network v ref v out r1 comp c cf r f c f r2 g m r a c a figure 4. type iii compensation network
max15036/max15037 boost converter compensation the boost converter compensation gets complicated due to the presence of a right-half-plane zero f zero,rhp . the right-half-plane zero causes a drop in-phase while adding positive (+1) slope to the gain curve. it is impor- tant to drop the gain significantly below unity before the rhp frequency. use the following procedure to calculate the compensation components. (see figure 4.) 1) calculate the lc double-pole frequency, f lc , and the right half plane zero frequency. where: target the unity-gain crossover frequency for: 2) place a zero at 0.75 x f lc . where r f 10k . 3) calculate c a for a target crossover frequency, f c : where c = 2 f c. 4) place a pole at f zero,rhp . 5) place the second zero at f lc . 6) place the second pole at 1/2 the switching frequency. improving noise immunity when using the max15036/max15037 in noisy environ- ments, adjust the controllers compensation to improve the systems noise immunity. in particular, high-fre- quency noise coupled into the feedback loop causes duty-cycle jitter. one solution is to lower the crossover frequency (see the compensation section). pcb layout guidelines careful pcb layout is critical to achieve low-switching power losses and clean stable operation. use a multi- layer board whenever possible for better noise immuni- ty. follow these guidelines for good pcb layout: 1) solder the exposed pad to a large copper plane under the ic. to effectively use this copper area as a heat exchanger between the pcb and the ambi- ent, expose this copper area on the top and bottom c c frc cf f sw f f = ? (. ) 205 1 () f rc p fcf 2 1 2 = r fc r lc a a 1 1 2 = ? () f rc z a 2 1 21 = r frc a zero hp a = 1 2 , () f rc p aa 1 1 2 = c vdlc rv a osc c out cfin = ? () + ? ? ? ? 1 2 2 c fr f lc f = 1 2075 . () f rc z ff 1 1 2 = f f c zero rhp , 5 d v v r v i in out min out out max =? = 1 () () f d lc f dr l lc out zero rhp min = ? = ? 1 2 1 2 2 , () () 2.2mhz, 3a buck or boost converters with an integrated high-side switch 20 ______________________________________________________________________________________
side of the pcb. do not make a direct connection of the exposed pad copper plane to the sgnd (pin 10) underneath the ic. connect this plane and sgnd together at the return terminal of the v+ bypass capacitor 2) isolate the power components and high-current paths from sensitive analog circuitry. 3) keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. 4) connect sgnd and pgnd together close to the return terminals of the v l and v+ high-frequency bypass capacitors near the ic. do not connect them together anywhere else. 5) keep the power traces and load connections short. this practice is essential for high efficiency. use thick copper pcbs to enhance full-load efficiency and power dissipation capability. 6) ensure that the feedback connection from fb to c out is short and direct. 7) route high-speed switching nodes (bst/vdd, source) away from the sensitive analog areas (bypass, comp, fb, and osc). use internal pcb layers for sgnd as emi shields to keep radiated noise away from the ic, feedback dividers, and the analog bypass capacitors. layout procedure 1) place the power components (inductor, c in , and c out ) first, with ground terminals close to each other. make all these connections on the top layer with wide, copper-filled areas (2oz copper recom- mended). 2) group the gate-drive components (boost diodes and capacitors, and v l bypass capacitor) together near the controller ic. 3) make the ground connections as follows: a) create a small-signal ground plane underneath the ic. b) connect this plane to sgnd and use this plane for the ground connection for bypass, comp, fb, and osc. c) connect sgnd and pgnd together at the return terminal of v+ and v l bypass capacitors near the ic. make this the only connection between sgnd and pgnd. max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch ______________________________________________________________________________________ 21
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch 22 ______________________________________________________________________________________ max15036 9 12 15 r7 15 d1 vl 13 14 16 r8 10k ju1 vl vl r9 10k pgood sgnd sync r10 10k c10 0.1 f 10 8 c9 4.7 f c8 0.1 f vl r5 6.04k 1% sgnd pgnd c7 0.22 f c6 0.1 f vin 7 11 6 5 4 c3 1200pf r4 10k 1% c4 22pf r3 750 1% c5 330pf r1 27.4k 1% r2 6.04k 1% vin pgnd + c1 47 f 35v vin vout c2 10 f 1 2 3 en reset sync bst/vdd source cko sgnd v l osc bypass pgnd v+ fb comp drain drain d2 l1 4.7 h c11 22 f vout vout pgnd c12 0.1 f figure 5. max15036 buck configuration
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch ______________________________________________________________________________________ 23 max15037 1 2 5 6 4 n1 3 r6 4.7 9 12 15 r7 15 d1 vl 13 14 16 r8 10k ju1 vl vl r9 10k pgood sgnd sync r10 10k c10 0.1 f 10 8 c9 4.7 f c8 0.1 f vl r5 6.04k 1% sgnd pgnd c7 0.22 f c6 0.1 f vin 7 11 6 5 4 c3 1200pf r4 10k 1% c4 22pf r3 750 1% c5 330pf r1 27.4k 1% r2 6.04k 1% vin pgnd + c1 47 f 35v vin vout c2 10 f 1 2 3 en pgood sync bst/vdd source dl sgnd v l osc bypass pgnd v+ fb comp drain drain d2 l1 4.7 h c11 22 f vout vout pgnd c12 0.1 f figure 6. max15037 buck configuration
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch 24 ______________________________________________________________________________________ figure 7. max15036 boost configuration max15036 ju1 v l pgood sgnd vin vout pgnd sync vin v l v l r1 27.4k 1% r2 6.04k 1% r4 22.1k 1% r8 10k r5 6.04k 1% r10 10k r9 10k 1 drain 2 drain 3 comp 7 v+ 6 bypass 4 fb 16 en 15 bst/vdd 12 source 9 cko 5 osc 13 sync 14 reset c10 0.1 f vin 11 pgnd c6 0.1 f v l c8 0.1 f 8 v l 10 sgnd c9 4.7 f sgnd pgnd d2 l1 4.7 h c2 10 f c3 2200pf r3 1k 1% c5 560pf c11 22 f c12 0.1 f c1 47 f 35v vout vout pgnd c4 22pf c7 0.22 f
max15036/max15037 2.2mhz, 3a buck or boost converters with an integrated high-side switch maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 ? 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. v+ drain output1 c in v in source clkout master sync sync clkout (master) source (master) source (slave) clkin duty cycle = 50% v+ drain source slave sync output2 sync phase clkout phase figure 8. synchronized converters 15 16 14 13 6 5 7 drain fb 8 drain pgnd dl source 1 + 2 pgood 4 12 11 9 bst/vdd en v l v+ bypass osc max15037 comp sgnd 3 10 sync thin qfn 5mm x 5mm top view ep* *exposed pad. pin configurations (continued) chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 16 tqfn t1655-2 21-0140

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